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Patent Searching and Data


Title:
CLOCK CONTROLLER
Document Type and Number:
Japanese Patent JPH08272478
Kind Code:
A
Abstract:

PURPOSE: To reduce the current consumption of every oscillation circuit itself by providing the oscillation circuits of plural systems and properly select these oscillation circuits according to the system operating conditions.

CONSTITUTION: Two oscillation circuits 11 and 12 are used for the low and high speed operations respectively. A clock control circuit 16 performs the ON/OFF control of both circuits 11 and 12 according to the system operating conditions. Therefore, the clock signal (CLK1) oscillated by the circuit 11 is supplied to a CPU 14 and a CPU peripheral circuit 15 respectively via a selector 13 as a system clock signal (SYSCLK) in a low speed operation mode. On the other hand, the circuit 12 is kept in a halt state by the oscillation control signal (CLK2BEN0) of the circuit 16.


Inventors:
NOMURA HIROSHI
Application Number:
JP6993695A
Publication Date:
October 18, 1996
Filing Date:
March 28, 1995
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F1/04; G06F1/06; G06F1/08; (IPC1-7): G06F1/04; G06F1/08
Attorney, Agent or Firm:
鈴江 武彦