To provide a clock conversion circuit in which clock signals including many jitters are inputted, the frequency of the clock signals is converted to the same or larger frequency and the jitters are drastically reduced.
The clock conversion circuit is provided with a voltage controlled oscillation circuit in which the frequency is changed by a prescribed control voltage, a first frequency dividing circuit for frequency-dividing the clock signals from the outside, a second frequency dividing circuit for frequency-dividing output signals for a PLL feedback loop from the voltage controlled oscillation circuit, a phase comparison part for generating phase difference signals based on the result of comparing frequency dividing signals from the first frequency dividing circuit and frequency dividing signals from the second frequency dividing circuit, and a loop filter for smoothing the phase difference signals and outputting them as a control voltage. The voltage controlled oscillation circuit constitutes a positive feedback oscillation loop by at least a SAW resonator for resonating at a prescribed frequency, a differential amplifier for oscillation, a differential amplifier for a feedback buffer, and a voltage controlled phase shift circuit for shifting input signals for a prescribed phase amount on the basis of the control voltage, and the output signals for the PLL feedback loop are outputted from the differential amplifier for the feedback buffer.
Fujitsuna Hideyoshi
Osamu Suzawa