PURPOSE: To prevent the off-set voltage of an operational amplifier from being increased by a clock stopping condition for a long time by adding respective multi-phase clock to one input of a two-input OR, which corresponds to the phase number of the multi-phase clocks, commonly connecting the other input, obtaining it as a reset terminal and respectively obtaining clock outputs from the respective two-input ORs.

CONSTITUTION: Both two-phase output clocks 1' and 2' are caused to be high level by causing a reset terminal 2 to be the high level when a multi-phase clock generating circuit 1 is in the stopping condition and the selecting switches of a switched capacitor circuit are closed. Thus, for an operational amplifier input in the switched capacitor circuit, both a plus input and a minus input are connected to a ground. Accordingly, even when a clock driver circuit is left for a long time in such a condition, unbalance is not generated in a pair transistor, which goes to be the input differential pair of the operational amplifier. Thus, the off-set of the operational amplifier can be prevented from being increased.