Title:
CLOCK DRIVER FOR SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS62180605
Kind Code:
A
Abstract:
PURPOSE: To obtain a signal whose state changes without causing a steep change by using a CMOS type resistance element.
CONSTITUTION: An input terminal IN is connected to a logical element inverter INV via a CMOS resistance RCMOS, and the input and output of the logical element inverter INV are connected via a capacitive element C. The CMOS resistance RCMOS consists of an N-channel transistor (TR) QN and a P-channel TR QP, gates of the TRs QN, QP are connected respectively to power supply lines V1, V2 and a resistance appearing between a source and drain of the TRs QN, QP is connected in parallel with each other.
Inventors:
SHINOZUKA TAKASHI
Application Number:
JP2312186A
Publication Date:
August 07, 1987
Filing Date:
February 04, 1986
Export Citation:
Assignee:
NEC CORP
International Classes:
H03K17/16; H03H19/00; H03K4/94; (IPC1-7): H03H19/00; H03K4/94; H03K17/16
Domestic Patent References:
| JPS62122417A | 1987-06-03 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)