PURPOSE: To control a data clock frequency to be coincident with the frequency of a forming clock signal even when the data clock frequency is widely deviated from the frequency of the forming clock signal by composing a clock forming circuit of a phase difference information output means, current limiting means, integrating means and forming clock signal output means.

CONSTITUTION: A phase difference information output means 11 is provided to compare the phase of a digital data signal S6 with the phase of a forming clock signal S5 and to output a phase difference information signal, which level is changed corresponding to phase difference, and a current limiting circuit 8 is provided to limit the respective maximum values of currents to flow-in and flow-out to a capacitor C2 although the phase difference information signal is inputted, the built-in capacitor C2 is charged/ discharged and the terminal voltage of the capacitor C1 is changed in response to the phase difference information signal. Then, an integrating means 9 is provided to output the integration information signal of the terminal voltage and a forming clock signal output means 10 is provided to output the forming clock signal S5 which frequency is controlled based on the integration information signal. Thus, even when the frequency of clock S6 is widely deviated from the frequency of the forming clock signal S6, the circuit is operated so that these frequencies can be made coincident.