CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE

Japanese Patent JP3690899

B2

PROBLEM TO BE SOLVED: To reduce the circuit scale of a clock generating circuit without changing any adjusting unit when precisely adjusted clocks are generated from one clock in a very small adjusting unit.
SOLUTION: When a clock generating circuit generates a plurality of clocks FCLK adjusted to the optimum phase at every one of a plurality of objects based on a received clock CLK, the circuit is provided with a first DLL circuit 21 which outputs a roughly adjusted clock RCLK by adjusting the delaying amount of the received clock CLK and a plurality of second DLL circuits 22-0 to 22-n which are respectively provided for each object and output a plurality of clocks FCLK by adjusting stepwise the delaying amount of the roughly adjusted clock RCLK. The first DLL circuit 21 changes the phase adjusting amount by discriminating whether the clock RCLK leads or lags the optimum phase within a prescribed phase difference and the second DLL circuits 22-0 to 22-n change the phase adjusting amount by discriminating whether the plurality of clocks FCLK lead or lag the optimum phase.

JPH06103762	INTERNAL VOLTAGE GENERATING DEVICE FOR DRAM
JPH06343260	CHARGE PUMP CIRCUIT
JPH11202958	VOLTAGE GENERATING CIRCUIT

Shinya Fujioka

JP14244197A

August 31, 2005

May 30, 1997

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富士通株式会社

G11C11/407; G06F1/10; G06F1/12; G06F13/42; G11C11/401; G11C11/4076; H03K5/13; H03K5/15; H03K19/0175; H03L7/081; H03L7/087; (IPC1-7): H03K19/0175; G06F1/10; G06F1/12; G06F13/42; G11C11/407; H03K5/13; H03K5/15

JP8097715A
JP6097788A
JP5100768A
JP3130678A
JP3064208A
JP10320075A

Takashi Ishida
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama

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