PURPOSE: To generate a clock whose frequency is not 1/2n without varying the frequency of an original oscillator, by providing a gate circuit which controls the passing of a part of an original clock between stages of a frequency divider.
CONSTITUTION: The output CLK of the original clock oscillator is inhibited from passing through a logical arithmetic circuit G2 during a period TH wherein the output OT1 of the 1st-stage frequency divider FF1 and the output OT2 of the 2nd-stage frequency divider FF2 are both at level H. Namely, the clock is frequency-divided to a half the original clock at the terminal of output OT1, and then divided to a quarter at the terminal output OT2, so one of four original clocks is cut off by the output of the arithmetic circuit G2. Further, the following stage FF3 performs 1/2 frequency division to obtain an output OT3 and an FF4 further performs 1/2 frequency division, so the duty ratio of the waveform approximates to 50% gradually, the clock is used suitably.
| JP3666078 | FREQUENCY DIVISION CIRCUIT |
| WO/2009/116399 | CLOCK SIGNAL DIVISION CIRCUIT AND METHOD |
| JPH04344711 | FREQUENCY DIVIDER |
OGATA YUUSUKE
MATSUYAMA HIROSHI
NARA TAKASHI
| JP39020589A | ||||
| JPS5518148A | 1980-02-08 | |||
| JPS551715A | 1980-01-08 | |||
| JPS56165422A | 1981-12-19 | |||
| JPS5765022A | 1982-04-20 |