Title:
CLOCK GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JP2015115633
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a clock generation circuit that reduces an increase in skew of a comparison clock relative to a reference clock caused by spectrum spreading while keeping a jitter characteristic intact.SOLUTION: The clock generation circuit of the present invention for generating and outputting an output clock on the basis of a spread-spectrum-frequency-modulated reference clock includes: a phase comparator for detecting a phase difference between the reference clock and a comparison clock corresponding to the output clock; a charge pump circuit for outputting a driving signal of a current amount controlled on the basis of the phase difference detected by the phase comparator and a current control signal; a voltage-controlled oscillation circuit for outputting the output clock having a frequency depending on the driving signal output from the charge pump circuit; and a skew adjustment circuit for generating the current control signal on the basis of a time variation in a value of skew between the reference clock and the comparison clock, and outputting the current control signal to the charge pump circuit.
Inventors:
EGAMI KOSUKE
Application Number:
JP2013254008A
Publication Date:
June 22, 2015
Filing Date:
December 09, 2013
Export Citation:
Assignee:
MEGA CHIPS CORP
International Classes:
H03L7/08; G06F1/10; H03K5/04; H03K5/26; H03L7/093; H03L7/18
Domestic Patent References:
| JP2009188811A | 2009-08-20 | |||
| JP2002043939A | 2002-02-08 | |||
| JP2012205046A | 2012-10-22 |
Foreign References:
| WO2007080719A1 | 2007-07-19 |
Attorney, Agent or Firm:
Patent Services Corporation m&s Partners
Hideaki Shioya
Akihiko Miyazaki
Hideaki Shioya
Akihiko Miyazaki