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Title:
CLOCK SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH0298212
Kind Code:
A
Abstract:

PURPOSE: To realize a circuit oscillated in itself synchronously with a signal inputted externally by constituting the title circuit with a control circuit outputting selectively a feedback signal with a control signal and plural inverter circuits in cascade connection receiving an output signal of the control circuit and supplying an output signal to a feedback signal input terminal.

CONSTITUTION: The circuit is provided with a NAND circuit which realizes a function united an inverter of a ring oscillator and a control circuit generating a control signal by using a control signal input signal line 100 and a feedback signal line 105 as input lines and inverters 12-15 connected in cascade with signal lines 101-104 for constituting the ring oscillator. Moreover, a circuit 16 to be synchronized is a circuit to be synchronized by a signal of a feedback signal line 105. Thus, a clock signal generating circuit oscillated in itself synchronously with the signal inputted externally is realized.


Inventors:
YAMASHINA MASAKATSU
GOTO JUNICHI
Application Number:
JP25105588A
Publication Date:
April 10, 1990
Filing Date:
October 05, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K3/02; H03K3/03; (IPC1-7): H03K3/02; H03K3/03
Domestic Patent References:
JPS49127553A1974-12-06
JP60108040B
JPS5416963A1979-02-07
JPS5726925A1982-02-13
JPS5360547A1978-05-31
JPS60250712A1985-12-11
Attorney, Agent or Firm:
Naoki Kyomoto