To easily deal with an optional signal transmission speed by adding a comparison signal divider means to a clock signal generation circuit to produce a signal of a desired frequency.

A reference signal extraction means 102 extracts a reference signal from an input signal 101, and a comparison signal generation means 103 produces a comparison signal for the phase comparison by using the output of a phase comparison means 105 as its input. The comparison signal is divided by a phase signal divider means 104 so as to secure the same frequency as the reference signal, and these divided comparison signals are supplied to the means 105. The means 105 compares the phase of the reference signal obtained by the means 102 with the phases of comparison signals divided by the means 104. These comparison results are fed back to the means 103. Then a clock signal 106 which is synchronous with the signal 101 is obtained by the means 104 via the function of a phase locked loop. Thus, it's possible to produce a clock signal in response to its optional transmission speed by using a divider of high accuracy to construct a PLL circuit.