To obtain highly reliable synchronous clocks with excellent frequency stability and phase followup ability.

An analog PLL circuit is composed of a reference clock oscillation circuit 13, a phase frequency comparator 14, a charge pump filter 16 and a voltage controlled ring oscillator 18. The voltage controlled ring oscillator 18 is composed by cascade-connecting the (n) stages {(n) is an integer equal to or more than 2} of inverter circuits IV0, IV1,...IVn in a ring shape and the internal clocks CK0, CK1,...CKm {(m) is the integer equal to or more than 2} of different phases are generated with a fixed pitch at taps between the respective inverter circuits. A phase comparator 10 and a selector 12 select the internal clock CKi whose phase is closest to a reference signal SEi from the plural pieces of the internal clocks CK1, CK1,...Ckm from the ring oscillator 18 as required so as to make the phase of the synchronous clock CKs follow up the phase of the reference signal SEi and output it as the synchronous clock CKs.