PURPOSE: To permit a clock multiplication part to oscillate stably by itself even if an input signal discontinues, by inhibiting the output signal of a clock extraction part with the output of an input signal break detection part in a clock circuit which multiplies a phse synchronous loop by extracting a timing clock from a received transmission code string.

CONSTITUTION: An input signal from input terminal 1 is supplied to tank circuit 22 via waveform equalizer 21 of clock extraction part 20 and also inputted to input signal break detection part 10. A clock output from tank circit 22 is inputted via AND circuit 40 to a clock multiplication part to multiply its frequency, obtaining output 3. When the input signal discontinues, output 4 of detecting circuit 10 is ceased and the output of tank circuit 22 is inhibited by AND gate circuit 40, but clock multiplying circuit 30 generates a stable self-oscillation output and is never influeced by noises, etc.