To accurately adjust the phases of a plurality of frequency dividing clocks of a plurality of slave circuits.
A clock synchronization circuit 18 is provided with a phase detection part 14, a clock adjustment part 15, a system clock generation part 16 and a control part 17. The system clock generation part 16 generates clocks SPUCK and HS2CK. The phase detection part 14 detects the phase states of the frequency dividing clocks RICK, GICK and BICK from image pickup sensors 2R, 2G and 2B, generates phase signals SD and outputs them to the control part 17. The control part 17 generates delay control signals ASEL corresponding to a difference between the phase of the frequency dividing clocks RICK, GICK and BICK and the phase of a reference clock SPUCK on the basis of the phase signals SD and outputs them to the clock adjustment part 15. The clock adjustment part 15 changes the phase of a supply clock HS2CK on the basis of the delay control signals ASEL, generates external clocks RP2CK, GP2CK and BP2CK and supplies them to the image pickup sensors 2R, 2G and 2B.
| JPH06338781 | SEMICONDUCTOR DEVICE |
| JP2013534744 | Methods and equipment for delay lock loops and phase lock loops |
Yoshitake Hidetoshi
Takahiro Arita
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