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Title:
CMI CODE DECODING CIRCUIT
Document Type and Number:
Japanese Patent JPS6268336
Kind Code:
A
Abstract:

PURPOSE: To decode correctly even a CMI code including 0 violation bit by counting a bit number subjected to violation and comparing it with a preset violation number and inverting the phase of a clock being the decoding of the CMI code.

CONSTITUTION: A 1 violation detection means 101 detects the violation of code 1 at a CMI code input. A 0 violation detection means 103 uses a clock selected by a clock selection means 102 to detect the code 0 violation. The output of 0 violation of the means 101 and the output of the 0 violation detection means 103 count the number of violations in one frame by a violation detecting means 104. A deciding means 105 compares the violation number counted by the violation count means 104 with the preset violation number and when they are dissident, the selection of the clock by the means 102 is inverted.


Inventors:
ITO KAZUHIKO
KATSUYAMA TSUNEO
HAYAMI SHICHIRO
Application Number:
JP20784385A
Publication Date:
March 28, 1987
Filing Date:
September 20, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L25/49; H03M5/04; H03M5/12; H04L7/00; H04L7/02; H04L7/08; (IPC1-7): H03M5/04; H04L7/00; H04L7/02; H04L7/08; H04L25/49
Attorney, Agent or Firm:
Kugoro Tamamushi