Title:
CMOS CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH07221629
Kind Code:
A
Abstract:
PURPOSE: To provide a CMOS circuit for reducing crosstalk noise and reducing power source noise.
CONSTITUTION: By providing feedback control circuits 11A and 11B for making the time required for switching MOS transistors P1 and N1 from an OFF state to an ON state longer than switching time from the ON state to the OFF state, preventing the mutually serially connected MOS transistors P1 and N1 from being simultaneously turned to the ON state and preventing a through current, the power source noise is reduced. Further, by increasing the rising time (tr) and falling time (tf) of output signals, the crosstalk noise is reduced.
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Inventors:
MARUYAMA TETSUYA
Application Number:
JP3546094A
Publication Date:
August 18, 1995
Filing Date:
February 08, 1994
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L27/04; H01L21/822; H01L21/8238; H01L27/092; H03K19/0175; (IPC1-7): H03K19/0175; H01L21/822; H01L21/8238; H01L27/04; H01L27/092
Attorney, Agent or Firm:
Tamamura Shizuyo