To suppress terminal voltage fluctuation by the temperature at a CMOS interface terminal, when an output current begins to flow.
A CMOS interface terminal 2 is connected to the bases of NPN transistors 3, 4, a resistor 9 is connected between emitters of the transistors 3, 4 and a resistor 10 is connected between the emitter of the transistor 3 and a ground terminal 11. A current detector circuit 20 detects the difference current between collector currents of the transistors 3, 4 and flows an output current I3 according to the difference current only when the difference current has a positive polarity. The size of the NPN transistors 3, 4 and the resistance values of the resistors 9, 10 are determined so that the terminal voltage at the CMOS interface terminal 2 is approximately equal to a band-gap voltage, when the collector currents of the transistors 3, 4 are equal.
Next Patent: PLL CIRCUIT AND CONTROL METHOD THEREFOR