To enable increase of the tolerance with respect to step fluctuation, without affecting PLL transfer characteristics.

In a PLL circuit having an ultra-low cutoff frequency not larger than 0.1 Hz, a gain in a primary loop gain portion 4 is forcedly increased in a phase lock mode so as to increase the step fluctuation tolerance. Namely, an offset value α is forcedly added to the output of a phase comparator 3 by using an offset adder 2. Because the step fluctuation tolerance (locking range) is determined by a dc loop gain, the forced offset value α is obtained from a step fluctuation width which is actually to be suppressed.