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Patent Searching and Data


Title:
CMOS MULTIPLIER
Document Type and Number:
Japanese Patent JPH10154194
Kind Code:
A
Abstract:

To suppress the circuit current and to attain a complete linear operation in a simple constitution by supplying plural tail currents to a transistor where plural specific triple tail cells form the input/output pairs and also to a constant current driven transistor to prevent these transistors from being cut off.

This multiplier is provided with a 1st triple tail cell which drives the transistors TR M1 and M2 forming an input/output pair and also a TR M3 which is driven by a constant current source Io by a common tail current, and a 2nd triple tail cell which drives the TR M4 and M5 forming an input/output pair and also a TR M6 which is driven by the current source Io by the common tail cell. Then the output pairs of these triple tail cells are connected together with crossing to each other with the input pairs connected in common to each other for input of a differential input signal Vx. At the same time, the TR M3 and M6 form an input pair for input of a differential input signal Vy. Then two tail currents are supplied to these TRs in order to prevent them from being cut off.


Inventors:
KIMURA KATSUHARU
Application Number:
JP32785896A
Publication Date:
June 09, 1998
Filing Date:
November 22, 1996
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; G06G7/164; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
Asato Kato