To obtain the same accuracy as before in a simple circuit structure.

This multiplier has a master clock means 1 which creates a synchronous clock that transmits and receives data, a frequency dividing means 2 which divides a clock of the means 1 several times and outputs each of them, a storing means 3 of data, another storing means 4 which stores a multiplication coefficient that is multiplied by data and a selecting means 5 which selects whether the data of the means 3 is outputted or not in accordance with the multiplication coefficient stored in the means 4 and the output frequency dividing signal of the means 2. Also, the means 5 has a selecting means 5a which selects either partial or entire operation results of plural frequency dividing signals in accordance with the multiplication coefficient of the means 4 or a fixed value and selects whether the data stored in the means 3 is outputted or not in accordance with the selection result.