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Title:
CMOS OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH05315560
Kind Code:
A
Abstract:

PURPOSE: To improve a CMOS output circuit in output characteristics by a method wherein a means which controls a PMOS and an NMOS output transistor in effective channel width and another means which enables the output transistors to generate control signals are provided.

CONSTITUTION: A primary component part is composed of a PMOS output transistor 4, an NMOS output transistor 5, effective channel width control means 6 and 7, and a control circuit block 3. When signals of H level and L level are inputted into control input terminals 9a and 9b respectively, the control circuit block 3 is degraded in drive capacity by one rank, and when signal of H level is inputted into both the terminals 9a and 9b, transistors 6T1 and 6T2 are turned OFF and the control circuit block 3 is kept low in drive capacity. When signal of L level is inputted into both the terminals 9a and 9b, transistors 7T1 and 7T2 are turned ON and the control circuit block 3 is kept high in drive capacity. By this setup, an output transistor can be controlled in current drive capacity.


Inventors:
MURAKAMI KAZUO
Application Number:
JP14826192A
Publication Date:
November 26, 1993
Filing Date:
May 13, 1992
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F3/00; H01L21/8238; H01L27/092; H03K17/687; H03K19/0175; H03K19/0948; (IPC1-7): H01L27/092; G06F3/00; H03K17/687; H03K19/0175; H03K19/0948
Attorney, Agent or Firm:
Kenichi Hayase



 
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