PURPOSE: To make the fault diagnosis of each part of the circuit efficient by inputting a constant check series independently of a logic function to each signal input line and a product term line control line of an AND matrix circuit and observing a parity signal outputted from a parity generating circuit.

CONSTITUTION: A regular check series independent of a logic function is given to signal lines 5, 27, 28 of a diagnostic input control circuit 22 and each product term line control line 25b of a diagnostic input product term line control circuit 25. In this case, number of sum term lines 24 giving a parity signal of a prescribed level from a parity generating circuit 26 of an OR matrix circuit 2 is subjected to parity check. Thus, a fault occurred in an AND matrix circuit 1 and the OR matrix circuit 2 is diagnosed efficiently by a simple circuit.