PURPOSE: To increase number of bits of a counter without decreasing the operating frequency by detecting overflow for each block and executing reload of a data.
CONSTITUTION: A critical path exists in a low-order block and has a maximum of 12 stages, and a load capacity to a reload signal RLDA is for four gates comprising flip-flops F1, F2 and two gates and it is constant independently of number of bits of a high-order block. Moreover, the critical path in the high-order block is ten stages and the load capacity is for five gates, then the reloading is slow, but since reloading of the high-order block has only to be executed while overflow takes place in the low-order block, no high speed operation is required toward the low-order block. Thus, the reload counter whose operating frequency is not lowered is obtained even if number of bits of the counter 1 is increased.
JP3031206 | FREQUENCY DIVIDING CIRCUIT |
JP2641964 | [Title of Invention] Divider |
JPH07141897 | SHIFT REDISTER |
HITACHI MICROCUMPUTER ENG