PURPOSE: To realize the CMOS variable frequency divider circuit with excellent operation stability and high speed operation at a GHz band even at a power supply voltage of nearly 1.5V by employing a complementary signal input output FF for a D-FF deciding the performance of the circuit.

CONSTITUTION: A complementary signal input output static FF with a large operating margin even under a low power supply voltage and very high speed operation is adopted for a D-FF. Then inverters 68, 69 and TG 72, 73, 74, 75 form master side FF elements and inverters 70, 71 and TG 76, 77, 78, 79 form slave side FF elements and the entire elements form a 1st-stage D-FF. Similarly, inverters 80, 81 and TG 84, 85, 86, 87 form master side FF elements and inverters 82, 84 and TG 88, 89, 90, 91 form slave side FF elements and the entire elements form a post-stage D-FF.