PURPOSE: To accurately control a frequency division value of a 2nd frequency divider being a component of the PLL circuit.

CONSTITUTION: A frequency division value of a 2nd frequency divider 5 is fluctuated with staticelectricity or a voltage drop or the like. The PLL circuit 1 is unlocked by the fluctuation. Then an additional circuit 20 is provided to the PLL circuit 1 to solve the problem. A signal detector 21 of the additional circuit 20 detects the leading and trailing of a phase error signal outputted from a phase comparator 6 and a counter 22 is used to count the phase error signal from the start of its leading till the trailing is detected. A frequency division control circuit 23 compares the count of the counter 22 with a count reference value written in a memory 24 and when the count is larger, a frequency division value set to the said 2nd frequency divider 5 is controlled.