PURPOSE: To reduce a hardware scale and to shorten processing time.

CONSTITUTION: A data generator 3 generates 2M pieces of M-bit data, the inspection bits of N bits are added to the M-bit data in an encoding circuit and the block code of (M+N) bits is generated. An error addition circuit 5 generates the random error of P bits to the block code and performs output as an error addition code. In a memory 2, the M-bit data are written with the error addition code as a write address. At the time of performing a decoding processing, the check bits of N bits are added to the transmission data of M bits, a block encoded block code string is received as a reception block code string and a shift register 1 accesses the memory with the block code as a read address for the respective block codes of the reception block code string and reads stored data as error correction data.