PURPOSE: To turn a selector to a parallel/serial conversion circuit capable of a high-speed operation by performing control so that the time period of selecting one input terminal is included in the time period in which an input signal value to the input terminal is established by a control means.

CONSTITUTION: Since the cycle of the exchange of input data to the selector 51 is twice the cycle of an operation in which the selector 51 switches output, it is recognized that the cycle of the operation in which the selector 52 switches the input terminal is twice the selector 51. Similarly, the cycle of the operation of the selector 54 is twice the selector 52 and the cycle of the conversion of the input data in the selector 54 becomes twice the cycle of the operation in which the selector 54 switches the output further. Also, data XO pass through the selector 54, and when the input terminal A of the selector 52 is selected, the data XO pass through the selector 52 and the selection of the input terminal A by the selector 51 is waited for. In such a manner, by the operation in which data signals are advanced stage by stage, the respective selectors transmit the signals to the next stage without storing delay from the previous stage.