PURPOSE: To prevent generation of a code from being stopped by setting an initial value based on a signal resulting from frequency-dividing a clock signal.

CONSTITUTION: Every time, e.g. 7 clock signals are inputted from a clock signal generating section 2, a set signal output section 4 outputs a set signal and sets an initial value to a code generating section 1. After codes outputted from the code generating section 1 go to '7', '3' and '5', even when values of a shift register go to all zero due to the effect of noise or the like, since the initial state is set based on a set signal from the set signal output section 4, the production of the code is not stopped and the relation of phase with that of a substantial code is not deviated.