PURPOSE: To produce a decoded picture signal at a high speed by processing plural bits of the picture signal as a word and producing picture signals for each word from initial and terminal word addresses and a bit address.

CONSTITUTION: An MH code signal C is converted into run length RL by a converting circuit 1000, and a byte data forming circuit 2000 produces a picture signal BD for each unit form the RL as well as an address signal SB which stores the signal BD into a memory 3000. The circuit 2000 contains a storage circuit for recording start byte and recording start bit addresses and a storage circuit for recording end bit and recording end bit addresses. In addition, a mask circuit multiplexer, an AU, a byte date generating circuit, etc. are provided. Then picture signals are produced for each word unit at a high speed from the initial and terminal word addresses and the bit address. Thus a decoded picture signal is obtained at a high speed.