COMBINATION LOGIC CIRCUIT TEST APPARATUS

Title:

COMBINATION LOGIC CIRCUIT TEST APPARATUS

Document Type and Number:

Japanese Patent JPS62217170

Kind Code:

A

Abstract:

This device and method for testing a combinative logic circuit (4), includes on the one hand a circuit generating test sequences (30) for applying test logic signals to N inputs of the combinative logic circuit and, on the other hand, an output circuit (5) to analyze the output signals of the combinative logic circuit. These test sequences are successively applied to each of the N inputs (E1, E2, E3 and E4) so that an alternating series, at least twice, of logic "1"'s and of logic "0"'s while a word of N-1 bits is applied to the other inputs to ensure the transmission of the said alternating series to the output of the combinative logic circuit.

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Inventors:

DANIERU BASUSHIERA
BERUNAARU KURUTOWA

Application Number:

JP61687A

Publication Date:

September 24, 1987

Filing Date:

January 07, 1987

Export Citation:

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Assignee:

PHILIPS NV

International Classes:

G01R31/3183; G06F11/22; G01R31/317; (IPC1-7): G01R31/28; G06F11/22

Attorney, Agent or Firm:

Akihide Sugimura

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