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Patent Searching and Data


Title:
INSPECTION METHOD FOR SEMICONDUCTOR CIRCUIT BOARD
Document Type and Number:
Japanese Patent JPS62217169
Kind Code:
A
Abstract:

PURPOSE: To inspect the defect of a TFT active matrix circuit board with high reliability in a short time by applying the control terminal of a semiconductor element with a voltage which increases or decreases the threshold voltage of the element and detecting a current conducted to one main terminal.

CONSTITUTION: A signal for detection whose voltage rise rate dVR/dt is constant is applied to a gate voltage input terminal 34a and a current (is) conducted through a source line 31a is detected by a current detecting circuit 36. Cin(on)/ Cin(off)>1 and iS=C1nldvR/dt, where Cin(off) and Cin(on) are composite values of electrostatic capacity viewed from the gate voltage input terminal 34a when the voltage value of a signal voltage VR is larger and smaller than the threshold voltage of a TFT (Thin Film Transistor) 30 and iS is the current. The current iS is converted into a voltage vS and vS(on)/vS(off), vS(on), and vS(off) and observed to perform defect inspection as to the TFT30, gate line and source line.


Inventors:
KITAJIMA MASAAKI
OWADA JUNICHI
SUZUKI MASAYOSHI
Application Number:
JP5919786A
Publication Date:
September 24, 1987
Filing Date:
March 19, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01R31/28; G01R31/317; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Katsuo Ogawa