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Patent Searching and Data


Title:
COMMUNICATION DEADLOCK AVOIDING DEVICE
Document Type and Number:
Japanese Patent JPH0652129
Kind Code:
A
Abstract:

PURPOSE: To shorten processing time for avoiding deadlock and to prevent the use efficiency of a processor from deteriorating.

CONSTITUTION: The number of messages accumulated in the message buffer 13 of a calculation processor 2 is checked. When the messages cannot be accumulated in the message buffer 13, the messages which are transmitted hereafter are returned to a transmission processor 1. Thus, possibility that deadlock in the calculation processor 2 occurs is eliminated. When the returned message is received, the new generation of the message in the transmission processor 1 is temporarily stopped, and the message accumulated in the message buffer 12 is retransmitted after a situation becomes that where deadlock does not occur. When the messages accumulated in the message buffer 12 are eliminated, the generation of the message is resumed.


Inventors:
KIMURA HIROAKI
Application Number:
JP22065292A
Publication Date:
February 25, 1994
Filing Date:
July 28, 1992
Export Citation:
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Assignee:
NIPPON STEEL CORP
International Classes:
G06F13/00; G06F15/16; G06F15/173; G06F15/80; (IPC1-7): G06F15/16; G06F13/00
Attorney, Agent or Firm:
Kokubun Takaetsu



 
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