To provide a comparator having hysteresis wherein high speed switching is enabled, without being accompanied by a large current consumption.
This comparator is provided with a first transistor (M1) and a second transistor (M2), whose gates form the inputs of the comparator. Main current paths of both of the transistors are connected to each other at one end. Further, the comparator is provided with a third transistor (M3) and to a fourth transistor (M4). A gate of the third transistor (M3) is connected to the gate of the first transistor (M1), and its main current path is connected from one end of main current paths of the first and the second transistors (M1, M2) to the other end of a main current path of the second transistor (M2) via a main current path of the fourth transistor (M4). A gate of the fourth transistor (M4) is connected to the output signal or an inverted output signal of the comparator. The comparator is used e.g. in an ASK demodulator of transponders.
BORUFUGANGU SHIYUTAINHAAGEN
OBERHUBER RALPH
URURITSUHI KAIZAA
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
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