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Patent Searching and Data


Title:
COMPILING PROCESSOR
Document Type and Number:
Japanese Patent JP3540837
Kind Code:
B2
Abstract:

PURPOSE: To distributedly arrange array data for actualizing parallelism without entailing an overhead of communication by providing an arrangement means which allocates divided array data to respective physical processors in a twisted state.
CONSTITUTION: When a detecting means 10 detects array data to be distributed and their dimensions, an allocating means 11 assumes (n×n) virtual processors in the case where the number of physical processors is (n) and the array data to be distributed are in two dimensions or (n×n×n) virtual processors in the case where the array data are in three dimensions. The array data detected by the detecting means 10 are allocated to those virtual processors according to prescribed algorithm while the dimensions detected by the detecting means 10 are regarded as decentralization dimensions. Then, when the object array data are allocated to the virtual processors through the processing of the allocating means 11, the arranging means 12 performs processing for allocating the array data on the virtual processors to the respective physical processors in the twisted state.


Inventors:
Tatsuya Shindo
Application Number:
JP10261094A
Publication Date:
July 07, 2004
Filing Date:
May 17, 1994
Export Citation:
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Assignee:
富士通株式会社
International Classes:
G06F9/45; G06F9/50; G06F15/16; (IPC1-7): G06F15/16; G06F9/45
Other References:
進藤達也、外4名,Twisted Data Layout,並列処理シンポジウムJSPP'94論文集,1994年 5月18日,p.161-168
J.M.Anderson and M.S.Lam,Global Optimizations for Parallelism and Locality on Scalable Parallel Machines,Proc. ACM SIGPLAN'93 Conf. PLDI,1993年 6月23日,p.112-125
Attorney, Agent or Firm:
Hikaru Okada
Yutaka Morita