Title:
COMPLEMENTARY CLOCK SYSTEM
Document Type and Number:
Japanese Patent JPH09321591
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a complementary clock system for an inverted clock signal in which a peak value and a time mean value of a load current flowing through a supply line are reduced without decreasing a signal processing speed. SOLUTION: This complementary clock system is provided with a clock generator 4 generating 1st and 2nd clock signals, a 1st drive stage 1 and a 2nd drive stage 2 having respectively 1st and 2nd clock lines 9.1, 9.2, and a current path 5 which is selected for the 1st clock line 9.1 or the 2nd clock line 9.2. Capacitor loads on the 1st and 2nd clock lines 9.1, 9.2 correspond to 1st and 2nd load capacitors c1, c2 respectively, the ON time of the current path 5 is controlled by a gate circuit 8 included in the switchable current path, the switchable current path 5 includes further inductive elements 7.1, 7.2, and the gate circuit 8 is conductive for a switching period of the 1st and 2nd clock signals.
Inventors:
FURANTSU OTSUTOO BITSUTE
Application Number:
JP34416696A
Publication Date:
December 12, 1997
Filing Date:
December 24, 1996
Export Citation:
Assignee:
ITT IND GMBH DEUTSCHE
International Classes:
H03K5/151; H03K17/16; (IPC1-7): H03K5/151
Attorney, Agent or Firm:
鈴江 武彦 （外４名）
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