To realize a phase comparator circuit in which power consumption is reduced by the use of a simple circuit configuration.
In this phase comparator circuit, a reference signal is given to a reset terminal of an RS flip-flop 2 and a 1st input terminal of a 4-input NOR gate circuit 1, an input signal whose phase is compared with a phase of the reference signal is given to the reset terminal of the other RS flip-flop 2 and a 2nd input terminal of the 4-input NOR gate circuit 1, an output signal of the 4-input NOR gate circuit 1 is given to a set terminal of the two RS flip-flop circuits 2, 3 and the output signal of the two RS flip-flop circuits 2, 3 is given to 3rd and 4th input terminals of the 4-input NOR gate circuit 1 respectively, and the phase of the input signal is detected by comparing the length of time when an output of the one RS flip-flop 2 is at a high level with a length of time when an output of the other RS flip-flop 2 is at a high level.
KATAKURA MASAYUKI
Next Patent: FUNCTIONAL SEMICONDUCTOR SWITCHING ARRAY DEVICE