Title:
複合型補正バッファの設計
Document Type and Number:
Japanese Patent JP2007520904
Kind Code:
A
Abstract:
According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.
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Inventors:
James Chandler
Zumkeir, John
Forestia, Arnaud
Zumkeir, John
Forestia, Arnaud
Application Number:
JP2006515361A
Publication Date:
July 26, 2007
Filing Date:
June 09, 2004
Export Citation:
Assignee:
Intel Corporation
International Classes:
H03K19/0175; H03K19/00; H03K19/0948
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito