PURPOSE: To enable for the low-speed analyzer to accept the operation data of the high-speed analyzer by inserting the fixed logic arithmetic circuit between the high-speed and low-speed differential analyzers.

CONSTITUTION: The serial-connected 2n-1 units of delay circuits DL1WDL3 delays by one interlation each the operation data output OUT of high-speed digital differential analyzer DAh featuring the interlation speed ratio of 2n. In addition, coefficient units F1WF4 which multiply the coefficient of 1/2n connected to the operation data output as well as to each output of delay circuits are provided, along with adder 4D which adds the output of each coefficient unit. These delay circuits, coefficient units and the adder are inserted between the operation data output of DAh and the operation data input of low-speed digital differential analyzer DAl. Thus, an extremely accurate reception of the operation data of DAh becomes possible for DAl.