To improve the processing capacity and data transfer capacity of element processors, to reduce the number of connection switches and to reduce the transmission delay of a data transfer route.

The element processors PE1-PE4 are provided with data input circuits IC1-IC4 and data output circuits OC1-OC4, which are mutually independent and which can simultaneously operate. In the connection of the data input circuit IC1-IC4 and the data output circuits OC1-OC4, the data input circuit IC of one element processor PE and the data output circuit OC1-OC4 of the other three element processors PE are connected through switches SW12-SW43. For transferring data from the element processor PE1 to PE2, the switch SW 21 is turned on and data from the output circuit OC1 is received in the input circuit IC2. For transferring data from the element processor PE3 of PE1, the switch SW 13 is turned on and data from the output circuit OC3 is received in the input circuit IC1.