To control respective access addresses from plural processors in the initialization processing of the multi-processor and to improve the speed of the initialization processing in the plural processors with a simple circuit.

In the multi-processor system provided with CPU 102 and 103, initialization programs corresponding to respective CPU are stored in the addresses which are individually allocated to CPU in ROM 105. CPU 103 is provided with an address translation part 104. The access address at the time of the initialization processing of CPU 103 is converted into an address where the initialization program of ROM 105, which corresponds to CPU 103. The address translation part 104 starts the execution of the conversion processing of the access address with a RESET signal when the initialization of the multi- processor system starts, and the conversion processing is stopped with the signal from CPU 103.