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Title:
CONTENT ADDRESSABLE MEMORY WITH READ/WRITE FUNCTION CAUSING NO INTERRUPTION OF CONTINUOUS RETRIEVAL CYCLE
Document Type and Number:
Japanese Patent JP2012074131
Kind Code:
A
Abstract:

To provide a content addressable memory (CAM).

The CAM includes a retrieval port 102b for performing retrieval operation in each clock cycle, and a maintenance port 103a for writing and reading data at an address position of the content addressable memory. Further, an interlock signal is available, and transmitted from the retrieval port to the maintenance port to set the time when the data is written to and read out of the content addressable memory, and consequently the retrieval operation is continuous in the respective clock cycles without being interrupted. It is preferred that the interlock signal is transmitted at the end time of the retrieval operation and at the start time of retrieval precharge operation. The maintenance port is configured to set up the writing operation at the start time of the clock cycles and to perform the writing operation at the end time of the retrieval operation and at the start of the retrieval precharge operation.


Inventors:
GIBSON G F RANDALL
RADU AVRAMESCU
Application Number:
JP2011260527A
Publication Date:
April 12, 2012
Filing Date:
November 29, 2011
Export Citation:
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Assignee:
CORE NETWORKS LLC
International Classes:
G11C15/00; G06F17/30; G11C29/00; G11C15/04; G11C29/14; G11C29/26
Domestic Patent References:
JPH06502737A1994-03-24
JPH1055683A1998-02-24
JPH10255486A1998-09-25
JPH11126486A1999-05-11
JPH1196773A1999-04-09
JPH02174000A1990-07-05
JPH06502737A1994-03-24
JPH1055683A1998-02-24
Foreign References:
US5859791A1999-01-12
US5859791A1999-01-12
Other References:
JPN6013043867; Jason Podaima, et al.: '" A Self-Timed, Fully-Parallel Content  Addressable Queue for Switching Applications "' Proceedings of the IEEE 1999 Custom Integrated Circuits Conference , 19990516, pp.239-242, IEEE
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki