Title:
制御装置、ユーザプログラムの実行制御方法、およびシステムプログラム
Document Type and Number:
Japanese Patent JP7379932
Kind Code:
B2
Abstract:
The present invention reduces the time required for detecting and correcting errors generated in a memory. A volatile memory (106X) is configured to store data (142) to which detection information (144X) for error detection is added, and to respond to whether or not an error occurs in a specified region determined on the basis of the data at a specified address and the detection information corresponding to the specified address in response to a read request. When an access control unit (204X) reads an instruction from the volatile memory (106X), if the volatile memory (106) responds that an error has occurred in a region where the read instruction is stored, the access control unit (204X) reloads the data in the region where the error has occurred from a backup memory (110X) to the volatile memory (106X), and reads the instruction from the volatile memory (106X) again.
Inventors:
Masaya Kudo
Noriaki Suzuki
Mitsuru Nakamura
Noriaki Suzuki
Mitsuru Nakamura
Application Number:
JP2019152913A
Publication Date:
November 15, 2023
Filing Date:
August 23, 2019
Export Citation:
Assignee:
Omron Corporation
International Classes:
G06F11/10; G05B19/048; G06F9/445; G06F11/14
Domestic Patent References:
| JP2178862A | ||||
| JP2003131955A | ||||
| JP63142449A |
Foreign References:
| WO2012172645A1 |
Attorney, Agent or Firm:
Patent Attorney Fukami Patent Office
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