Title:
CONTROL METHOD FOR ELECTRONIC SYSTEM AND CONTROLLER
Document Type and Number:
Japanese Patent JP3490403
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for adjusting the operation margin or timing margin of the clocked system of a digital computer or a memory controller or the like.
SOLUTION: The initial frequency or default frequency of a clock is set and the clock control settings of a duty cycle, a VCO range and a gain, etc., are also initialized and set as some kinds of defaults. Tests such as ABIST, LBIST or other function tests, etc., are executed to the clocked system and the clock frequency is increased until failing in the test. At the time of failing in the test, one or plural clock control settings are adjusted and the test is executed again at the frequency in which a fault is generated. The test is repeated while increasing the frequency until failing in the test or reaching a desired timing margin.
Inventors:
Patrick Lee Rothno
James david strom
James david strom
Application Number:
JP2001070075A
Publication Date:
January 26, 2004
Filing Date:
March 13, 2001
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F1/04; G06F1/08; G01R31/319; G06F1/32; G11C29/50; (IPC1-7): G06F1/04; G01R31/319
Domestic Patent References:
| JP8315598A | ||||
| JP200036200A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)
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