SERIAL/PARALLEL CONVERSION CIRCUIT, DATA TRANSFER CONTROLLER, AND ELECTRONIC EQUIPMENT

Japanese Patent JP3580242

B2

PROBLEM TO BE SOLVED: To provide a serial/parallel conversion circuit, a data transfer controller, or the like, which combines serial/parallel conversion function with a buffer function to smooth out clock frequency differences.
SOLUTION: The serial/parallel conversion circuit (elasticity buffer) comprises a data-holding register 50, which holds serial data DIN input with a CLK1 (480 MHz) in a HS mode of the USB 2.0; a discrimination circuit 60, which discrimination between the effectiveness and non-effectiveness of the held data of a data cell, and a selector 66, which outputs data in the data cell discriminated as being valid from the data-holding register 50 with a CLK2 (60 MHz) of a lower frequency than the frequency of the CLK1. A data cell, the data of a head bit in which is discriminated as effectiveness, is regarded as being valid at the next clock cycle of the CLK2. The data cell is discriminate between validity and non-validity by each every clock cycle of the CLK2, then if the data cell is discriminated as non-effectiveness, outputting of the data of the data cell is waited for one clock cycle. A writhing pulse signal is generated to operate the data holding register 50 and a data status register 52.

Yoshiyuki Kamihara
Takuya Ishida

JP2000325341A

October 20, 2004

October 25, 2000

Click for automatic bibliography generation  

Seiko Epson Corporation

G06F5/00; G06F5/06; G06F13/00; H03M9/00; H04J3/06; (IPC1-7): G06F5/00; H03M9/00

JP4270515A
JP9034832A
JP11015636A

Inoue Ichi
Yukio Fuse
Mitsue Obuchi

Previous Patent: EQUIPMENT FOR MANUFACTURING HOT-DIP GALVANIZED STEEL SHEET

Next Patent: DIGITAL VIDEO/AUDIO RECORDING AND REPRODUCING DEVICE