PARALLEL/SERIAL CONVERSION CIRCUIT

Title:

PARALLEL/SERIAL CONVERSION CIRCUIT

Document Type and Number:

Japanese Patent JP2004135187

Kind Code:

A

Abstract:

To provide a parallel/serial conversion circuit having a plurality of parallel/serial converters, which can shorten the time necessary for perform parallel/serial conversion and can suppress expansion of the circuit scale.

The parallel/serial conversion circuit 10 includes two-channel parallel/serial converters 11a, 11b and a clock generator 12. If a parallel data signal 7a of the parallel/serial converter 11a has a frequency Fpa (Hz), a bit number for the parallel data signal is Na (bit), a frequency Fpb (Hz) for a parallel data signal 7b of the parallel/serial converter 11b is, and the parallel data signal 7b has a bit number Nb (bit); the clock generator 12 oscillates a clock signal 5, having a fixed frequency higher than Fpa × Na (Hz) and Fpb × Nb (Hz) and moreover nearly equal thereto.

Inventors:

OSHIRO NOBUHISA

Application Number:

JP2002299570A

Publication Date:

April 30, 2004

Filing Date:

October 11, 2002

Export Citation:

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Assignee:

SHARP KK

International Classes:

G06F5/00; H03M9/00; (IPC1-7): H03M9/00; G06F5/00

Attorney, Agent or Firm:

Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko

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