To accelerate the operation of the preamplifier of an A/D converter and then to reduce its power consumption and occupation area.

This A/D converter has a resistance ladder 1, a comparator 3, an encoder 4, and an input buffer 5. The comparator 3 consists of a switch SW1 connected to the output Vin of the input buffer 5, switch groups SW31 to SW3n to which reference voltages Vref1 to Vrefn are inputted in order, a charge capacitor C which is connected to an output terminal connected to the switch SW1 and SW31 to SW3n in common, and an amplifier AMP which has it input and output connected through the SW2. The amplifier AMP of the comparator 3 compares the sequentially inputted reference voltages Vref1 to Vrefn with the input signal Vin the decides that the input voltage Vin is higher than the reference voltage once the output of the AMP is inverted from 0 to 1. Since only a single charge capacitor C and a single amplifier AMP are needed, the input capacity of the comparator viewed from the input buffer 5 is reducible to accelerate the operation of the input buffer and then reduce the occupation area and power consumption of the A/D converter.