ANALOG/DIGITAL CONVERTER

Japanese Patent JPH1093438

A

To obtain an economical device executing high bit rate decoding and high speed operation by allowing a comparator to consist of two units, to select an input voltage and a reference voltage, to join to mutual inverters and to compare the voltage.

This analog digital converter is provided with the comparator with first and second units. In addition, the first and second nodes of each units are provided with capacitors C1, C2, first switches 80, 84 and second switches 81 and 85 selecting the input voltage V IN and the reference voltage V REF. In addition, each node is provided with first and second inverters 76 and 79 to output output signals. Switches 88 and 89 for connecting the outputs of the first and second inverters 76 and 79 to the second and first nodes of respectively the other unit are provided. By selecting the input voltage and the reference voltage to join mutual inverters to compare voltage like this, an economical device executing high bit rate decoding and high speed operation is obtained.

CLAYDON ANTHONY PETER J
CHARLES D MACFARLANE
GAMMACK RICHARD J
JONES ANTHONY MARK
ROBBINS WILLIAM P
MARK BARNES

JP11857297A

April 10, 1998

April 03, 1997

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DISCOVISION ASS

H04N7/26; H03H17/02; H03H21/00; H03K5/24; H03M3/02; H03M13/00; H03M13/15; H03M13/27; H04B3/06; H04L1/00; H04L7/00; H04L7/04; H04L25/03; H04L25/06; H04L27/02; H04L27/06; H04L27/227; H04L27/38; H04N5/00; H04N5/21; H04N5/44; H04N5/455; H04N5/52; H04N7/24; H04N7/30; H04N21/2383; H04N21/438; H04L7/033; H04L27/00; (IPC1-7): H03M3/02; H03H17/02; H03H21/00; H04B3/06; H04L27/06

Yoshiaki Ito

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