PURPOSE: To save the transfer of an instruction address by providing a coprocessor execution address detection device consisting of an instruction address storage device, an instruction identification device and an instruction address abandonment device.

CONSTITUTION: The instruction address storage device 13 sequentially stores instruction addresses 18 through an address bus 7 whenever MPU fetches an instruction. At that time, an instruction address identifier 19 by an instruction identification signal 17 are stored together. The instruction address 18 whose execution terminates is abandoned in accordance with a signal 16 and the identifier 19. When an exception, an interruption and a trap occur on the other hand, the selected address is outputted to an internal data bus 20. An instruction address abandonment device 14 outputs the abandonment signal 16 for abandoning the address 18 by a status signal 5 and the like. The instruction identification device 15 decodes the instruction fetched from a data bus 8 and gives the identifier 19 to the address 18 when the instruction is the coprocessor instruction. Thus, the transfer of the instruction address is saved and the processing speed improves.