PURPOSE: To eliminate the need for estimating a value possibly set as a count in advance by providing a NAND circuit which generates an n-bit select signal selecting the setting of a count and a reset signal to a counter based on an output of each selector to the system.

CONSTITUTION: When a pulse signal with a width of 5T is outputted from a terminal DOUT, 0, 1, 0, 0 are set respectively as count number setting signals S0, S1, S2, S3 and a pulse whose level 1 and whose width is 1T is inputted to a terminal DIN, then number of times of input of clock pulse is counted from the next clock pulse, and a reset signal 26 of the counter reaches 0 after lapse of a time 4T and a counter output signal storage register 31 is reset after a time 5T. That is, an optional value for the count from 0 up to 15 and for the width of the pulse signal outputted from the terminal DOUT from 1T up to 16T is set by the switching of the count number setting signals S0, S1, S2, S3.