To improve an access speed to a sequential data block.

A counter circuit 10 generates selectively count sequence in a binary count mode and an interleave count mode. A counter 16 is composed of three T flip-flops. A toggle control signal is supplied by a toggle control circuit 20, and the toggle control circuit 20 is provided with a logic gate made be enabled or be disenabled based on the state of a mode selection signal Select. In the binary mode, an output bit is used for switching a higher rank count stage. In the interleave mode, a binary toggle control signal is interrupted, and another counter circuit counts the toggle control signal by interleave sequence, and the toggle control signal is sent to a toggle input of a main counter by the toggle control circuit 20. The another counter circuit is reset according to a reset signal inputted to a load approval terminal.