PURPOSE: To offer a counter circuit for realizing a counting operation executed at a high speed and surely by allowing it to execute, in parallel the operations of an increment and a decrement while preceding an increment or decrement instructing signal, and selecting one of them with the instructing signal.

CONSTITUTION: By synchronizing with a first clock pulse, an increment instructing signal is inputted, and inputted to a flip-flop circuit FF1. Subsequently, unless a decrement instructing signal is inputted in a first clock period, it is synchronized with a second clock pulse, and inputted to a flip-flop circuit FF2. Thus, from a second clock period, an increment transfer signal becomes a high level. Unless the decrement instructing signal is inputted even in this second clock period, an increment counting operation executing signal +1 is formed from a gate circuit G2, and by synchronizing with a third clock pulse, the counter executes an increment operation.